1. Field of the Invention
The invention relates to the field of semiconductors, and in particular, to an efficient, high-performance field effect transistor.
2. Related Art
Modern semiconductor devices are continually being reduced in size to improve integrated circuit (IC) capabilities and performance. Smaller devices enable greater device density in an IC, thereby enabling the implementation of increased functionality in a reduced area. Unfortunately, this continued scaling of device geometries can also result in undesirable device characteristics.
For example, as a metal-oxide-semiconductor (MOS) transistor is scaled, the supply voltages provided to that MOS transistor must be reduced to prevent physical damage to the device. Consequently, the gate oxides of such scaled transistors must be made thinner and thinner to so that proper transistor action is maintained. However, a thinner gate oxide can result in increased subthreshold and band-to-band tunneling (BTBT) leakage currents (e.g., leakage current between the drain and bulk (substrate)). These leakage currents can undesirably increase power consumption and can also negatively impact device reliability. In addition, such leakage currents can turn on parasitic transistors in complimentary metal-oxide-semiconductor (CMOS) ICs, thereby causing latchup and weakening or even destroying the affected devices.
Accordingly, it is desirable to provide a structure and method for creating a scalable MOS transistor that minimizes leakage currents.